Si2’s Open Modeling Coalition Approves Statistical Library Format Extensions in ECSM Standard for Design Libraries

- Open Modeling Coalition continues on Roadmap -

Austin, Texas (June 4, 2007) - The Silicon Integration Initiative’s Open Modeling Coalition has approved the Effective Current Source Modeling (ECSM) Version 1.3 specification, which includes extensions for Statistical Library Format extensions. The new version of ECSM will be released as an Si2 specification after a 60-day patent exclusionary period which started on May 25, 2007. At the end of that period, the new version of ECSM will become available to the broad electronics industry, both users and EDA vendors alike, regardless of Si2 membership.

Continuing to build on the popular ECSM timing, noise, and power modeling format, addition of the statistical library format extensions makes the ECSM open standard the most advanced modeling format available. The statistical extensions release is the result of a joint submission by Cadence Design Systems, Magma® Design Automation Inc. and Extreme DA with support from Altos Design Automation, ARM and Virage Logic to the Si2 Open Modeling Coalition (OMC) made in October of last year. Additional work on the statistical extensions was provided by Intel, Freescale, and Sun Microsystems. This effort to quickly converge on a single open-standard statistical modeling format will facilitate the deployment of innovative statistical analysis technologies and enables greater design tool interoperability.

“The OMC is working to provide open standards for statistical modeling formats for design tools,” said Timothy Ehrler, OMC chair and senior manager of CAD Global Infrastructure at AMD. “We again see the on-schedule delivery of another important phase of a library modeling system and standard resulting from this collaborative effort by EDA, IP, and IDM industry leaders.”

The ECSM statistical extensions accurately model the impact of process and environmental variation – a potentially performance depriving problem – which can negate many of the advantages of moving to process nodes at or below 65nm. Using a statistical approach to timing analysis allows designers to unlock the true potential of smaller process technologies by reducing the pessimism that can rob chip performance in traditional design methodologies. The key to the ECSM statistical standard is that it uses sensitivities to process and environmental device parameters to holistically model variations around the nominal. The statistical format is the most complete available and accurately accounts for global, within the die and random variation. The net result – fewer analysis corners, increased chip performance, and better silicon.

“This newest extension to ECSM addresses a critical need of our leading-edge member companies to effectively and accurately model manufacturing process variations in design.” Says Sumit DasGupta, sr. vice president of Si2. “ This capability is essential for our customers to stay on-board the ITRS roadmap and capitalize on the capabilities offered by the latest technology nodes.”

This new ECSM technology will be demonstrated at the Design Automation Conference, June 3-7, in San Diego, CA. Altos Design Automation (Booth 1260) will be demonstrating Variety^tm which already supports the statistical extensions to ECSM. Cadence (in the Si2 Booth 5362) will also be demonstrating the technology as implemented in their new Encounter Timing System.

“The major roadblocks to adoption of statistical timing are characterization performance and lack of a standard library format.” Says Jim McCanny, CEO of Altos Design Automation, Inc. “ Altos is committed to removing these bottlenecks with on-going support for Si2’s approved statistical library format.”

About the Open Modeling Coalition (OMC)

The OMC technical objectives are to define a consistent modeling and characterization environment in support of both static and dynamic library representations for improved integration and adoption of advanced library features and capabilities, such as statistical timing. The system will support delay modeling for library cells, macro-blocks and IP blocks, and provide increased accuracy to silicon for 90nm and 65nm technologies, while being extensible to future technology nodes. Member companies are: Advanced Micro Devices (NYSE: AMD), Altos Design Automation, ARM (Nasdaq: ARMHY), Cadence Design Systems (Nasdaq: CDNS), Extreme DA, Freescale (NYSE: FSL), IBM (NYSE: IBM), Intel (Nasdaq: INTC), LSI Logic (NYSE: LSI), Nangate A/S, NXP Semiconductors, Renesas Technology Corp., Silicon Navigator, ST Microelectronics (NYSE:STM), Sun Microsystems (Nasdaq: SUNW), and Virage Logic (Nasdaq: VIRL). For more information on the OMC, visit: www.si2.org/?page=430

About Si2

Si2 is an organization of industry-leading semiconductor, systems, EDA and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time-to market, reduce costs, and meet the challenges of sub-micron design. Si2 is uniquely positioned to enable collaboration through a strong implementation focus driven by its member companies. Si2 focuses on developing practical technology solutions to industry challenges. Si2 represents over 100 companies involved in all parts of the silicon supply chain throughout the world.

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