Altera Selects Altos’ Liberate for Ultra-Fast
Characterization of 40nm HardCopy ASICs
San Jose, California – March 2, 2009 -
Altos Design Automation Inc. today announced that Altera Corporation has
adopted its Liberate cell characterization solution for use at 40nm. Altera will use Liberate to characterize
their own specialized library cells for use in Altera’s HardCopy®
III and HardCopy IV ASIC families.
Eugene Chen, director of CAD at
Altera, Corporation., said, “Our HardCopy III and HardCopy IV families offer an ideal solution for high-end digital applications
in several markets, including wireless and wireline communications, military
and broadcast”
Chen continued, “We selected Liberate because we needed to be able to
re-characterize our own custom cells so that they are optimized for our 40-nm
HardCopy ASICs. In particular, we needed
to be able to generate advanced current source models for timing, noise and
power.”
Jim McCanny, Altos CEO and founder
said, “A simple way to ensure that your designers get the most out of the
advanced process technology is to tune the characterization of the standard
cell library to match the target application” McCanny continued, “Using
Liberate, Altera will be able to easily characterize their most advanced cells
in conjunction with commercial libraries in a consistent and highly efficient
manner.”
About Liberate
Liberate
is an ultra-fast library creator that generates electrical models in Liberty®,
Verilog, Vital and IBIS formats. Liberate supports all the latest models for
timing, noise and power such as CCS (Composite Current Source) and ECSM (Effective
Current Source Models) Liberate also
supports ultra low power and high speed design styles that include power gating
cells, state retention registers, level shifters, pulse clocking and CML.
About
Altos
Altos Design
Automation provides ultra-fast, fully-automated characterization technology for
the creation of library views for timing, signal integrity and power analysis
and optimization. Altos advanced
modeling solutions are used by both corner-based and statistical-based design
implementation flows to reduce time to market and improve yield.
Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 4020 Moorpark
Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056. On the Web at: http://www.altos-da.com
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