Altos’
Statistical Timing Library Models Proven on UMC’s 65nm
Process using Extreme DA’s GoldTime
Variety™ LX characterizes UMC’s 65nm standard cell
library for sensitivity to process variations
The qualification process
involved the creation and validation of statistical timing models created by
Variety LX accounting for process parameter variation. UMC then performed
statistical timing analysis on critical signal paths using Extreme DA’s
GoldTimetm and all paths
were found to have good correlation to the golden Monte Carlo SPICE simulation
results. The mean path delay and mean plus /minus sigma path delay were well within
acceptable error tolerance levels.
“Statistical timing analysis can help reduce margins and
improve design productivity when using 65-nanometer processes where chip
performance is sensitive to parameter variations,” said Darsun Tsien,
UMC’s vice president of design methodology. “A working
statistical design flow needs library models that are derived from
statistical-based process models along with silicon derived parameter variation
measurements. We have confirmed that
Variety LX can efficiently generate accurate models required by downstream
statistical timing tools such as Extreme’s DA GoldTime
which enables improved yield prediction and optimization of circuit
performance.”
Jim McCanny, Altos CEO said, “By collaborating with UMC and Extreme DA in creating qualified statistical models, we have jointly created the foundation for our common customers to enjoy the benefits of using statistical design methods such as faster timing closure and lower power.”
"Statistical timing analysis relies on detailed
characterization of variations in the cell libraries used by designers,"
said Mustafa Celik, president and CEO of Extreme DA. "Our collaboration
with Altos and UMC has produced a powerful, verified statistical flow that can
improve IC performance and remove design pessimism. We are satisfying fabless
semiconductor companies’ demands for faster, more accurate timing closure and
higher chip yields.”
About Altos’ Variety LX
Variety creates statistical
timing cell models that represent the non-linear impact of any number of
systematic and random parameter variations.
All library timing data is characterized for variation including delays,
transitions, timing constraints and pin capacitances. Variety generates SSTA
models for a number of commercial SSTA products from a single characterization
run.
GoldTime™ provides timing analysis
for performance sign-off of integrated circuit (IC) designs manufactured in
advanced nanometer (nm) processes. With
its unique, patent-pending ThreadWave™ technology, GoldTime delivers 5X better speed and capacity over popular
solutions in use today. GoldTime works with both nominal and statistical model
libraries and supports corner-based and statistical design flows. See http://www.extreme-da.com for more
information.
About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that
manufactures advanced system-on-chip (SoC) designs for applications spanning
every major sector of the IC industry. UMC's SoC Solution Foundry strategy is
based on the strength of the company's advanced technologies, which include
production proven 90nm, 65nm, mixed signal/RFCMOS, and a wide range of
specialty technologies. Production is supported through 10 wafer manufacturing
facilities that include two advanced 300mm fabs; Fab 12A in
About Altos
Altos Design Automation provides ultra-fast, fully-automated characterization
technology for the creation of library views for timing, signal integrity and
power analysis and optimization. Altos’ advanced modeling solutions are used by
both corner-based and statistical-based design implementation flows to reduce
time to market and improve yield.
Privately held, Altos was founded in 2005 in