ALTOS AND CADENCE JOINTLY QUALIFY STATISTICAL TIMING MODELS FOR 45 and 65 NANOMETER PROCESSES

Altos Variety characterization tool qualified to generate S-ECSM libraries for

Cadence Encounter Timing System GXL and SoC Encounter System GXL

San Jose, California – September 30, 2007 - Altos Design Automation Inc. and Cadence Design Systems, Inc. today announced that they have qualified 45nm and 65nm statistical static timing analysis (SSTA) models generated by Altos Variety^tm in S-ECSM format for use with the new statistical timing analysis technology in the Cadence^® Encounter^® Timing System and SoC Encounter™ RTL to GDSII system.

The collaborative effort between Cadence and Altos involved the creation and validation of SSTA models by comparing a large number of paths reported by the Encounter Timing System, using cell models created by Variety^tm against SPICE-level Monte Carlo simulations. The test structures used to qualify the flow came from a number of different customers using different foundries. This collaborative effort was facilitated through the Cadence Connections® program.

Both the 45nm and 65nm models were validated, as well as inter-cell systematic variations and intra-cell random variations. This joint effort provides a critical element in the statistical design flow that gives designers much more accurate modeling of both on- and off-chip process variations. Without accurate variation models, designers resort to guard banding that, in turn, leads to expanded design schedules and larger chip area, with increases in both dynamic and leakage power consumption.

“The Altos Variety characterization tool produces highly-accurate statistical cell models in very reasonable runtimes, comparable to many existing non-statistical characterization tools,” said Jim McCanny, Altos CEO. “Our joint working relationship with Cadence ensures that the S-ECSM models Variety generates are optimal in terms of accuracy and data size so that they can be easily utilized by the Encounter Timing System.”

“With Encounter Timing System GXL and SoC Encounter GXL, Cadence delivers complete statistical analysis, optimization and characterization in a single environment,” said David Desharnais, product marketing group director at Cadence Design Systems. “In addition, our partnership with Altos and joint customers has enabled us to utilize Altos as another qualified source of statistical cell models for the Encounter digital IC design platform.”

About the Cadence Connections Program

The Cadence Connections program, which has more than 130 members, promotes interoperability by supporting open industry standards and working with third-party EDA vendors to create cohesive interfaces into the Cadence design environment.

About Variety

Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints and pin capacitances. Variety generates SSTA models for a number of commercial SSTA products from a single characterization run.

About Altos
Altos Design Automation provides ultra-fast, fully-automated characterization technology for the creation of library views for timing, signal integrity and power analysis and optimization. Altos advanced modeling solutions are used by both corner-based and statistical-based design implementation flows to reduce time to market and improve yield. 

Privately held, Altos was founded in 2005 in Santa Clara, CA. Its corporate headquarters is at 4020 Moorpark Ave., Suite 100, San Jose, CA 95117. Telephone: (408) 980-8056. On the Web at: http://www.altos-da.com

About Cadence
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence and Encounter are registered trademarks of Cadence Design Systems, Inc, and the Cadence logo is a trademark of Cadence in the United States and other countries.

Variety is a trademark of Altos Design Automation, Inc. All other trademarks and registered trademarks are the property of their respective owners.