Altos Design Automation


Jim McCanny, CEO & Founder

Prior to Altos, Jim was the Timing and Signal Integrity Marketing Group Director at Cadence. He was the VP of Marketing and Business Development at CadMOS when they were acquired by Cadence in 2001. Before CadMOS, Jim was Executive VP at Ultima Interconnect Technology (which as Celestry was acquired by Cadence in 2003), Major Account Technical Program Manager at EPIC Design Technology (which IPO'ed in 1994) and a Member of Group Technical Staff at Texas Instruments. Jim holds a BS in Math/Computer Science from Manchester, UK and has 30 years experience in EDA.

Ken Tseng, CTO & Founder, General Manager Altos China

Prior to founding Altos, Ken was a Cadence Architect responsible for signal integrity analysis tools PacifIC and CeltIC. At CadMOS, Ken was an R&D Director and the original author of CeltIC. Prior to that, he held R&D positions at Synopsys, Logic Modeling, Zycad and AMD. Ken holds multiple patents in timing, signal integrity and microprocessor design. He is an expert in circuit analysis, logic abstraction and signal integrity. He holds an MSEE/BSEE from UT Austin and has 25 years experience in EDA.

Kevin Chou, VP R&D & Founder

Kevin was a Senior Member of Consulting Staff at Cadence prior to founding Altos, responsible for the signal integrity closure flow in SoC Encounter. At CadMOS he was responsible for RLC interconnect analysis and CeltIC's cell noise library creation (cdB). Prior to CadMOS, Kevin held research positions at Princeton University, the Army High Performance Computing Research Center and Cornell Medical School. Kevin received his BSEE with summa cum laude from Cooper Union and his MSEE from Stanford University. Kevin has 15 years experience in EDA.

John Ennis, Worldwide VP of Sales

John joined Altos from Pyxis Technology where he was VP of Business Development. John started his career at Rockwell International as Sr. Design Engineer followed by a Design Management position at Analog Devices. In 1986 John began selling CAE software at Cadence and managed to exceed 100% of quota over a period of 8 years. After Cadence, John became VP of Sales (TCAD Division) at Avant!/TMA which was later sold to Synopsys. John has also held VP of Worldwide Sales positions at Circuit Semantics and Anchor Semiconductor. John holds a B.S. degree in Electrical Engineering, Summa Cum Laude, from the University of Trenton State John has over 28 years of sales experience.

Doug Roston, VP Applications

Doug was the Director of Core Comp for Signal Integrity at Cadence where he supported the Encounter Timing System, CeltIC, PacifIC, VoltageStorm, and Fire & Ice. At CadMOS he was the Applications Manager responsible for supporting world wide sales. Prior to CadMOS, Doug worked at Epic Design Technology where he supported major accounts. Doug has 25 years experience working in test, design and applications engineering with 25 years of that in EDA. Doug has a Bachelors degree in Mathematics and Computer Science from Vanderbilt University.

Wenkung Chu, Architect R&D & Founder

Wen was a Senior Member of Consulting Staff at Cadence prior to founding Altos, responsible for the mixed signal integrity analysis tool SeismIC. Prior to CadMOS, he worked at Cadence developing Virtuoso XL and ADE (Analog Design Environment). Wen has also worked as a custom designer and EDA lecturer at the HsinChu Science Park, Taiwan. He has 21 years experience in EDA.

Rob Galluzzo, North America VP Sales,

Rob has held senior sales positions at CadMOS, Synopsys, EPIC Design Technology (where he was the Intel Major Account Manger), Mentor Graphics, Silvar Lisco and SGI. Rob holds a BS from Rutgers and a MS from UC Berkeley. Rob has over 20 years experience in EDA Sales.


Copyright © 2006
Altos Design Automation Inc.