Related Links
Si2: Statistical Methods for Semiconductor Chip Design
Who needs statistical timing?
How low can you go?
Cell model creation for statistical timing analysis
Practical Applications of Statistical Static Timing Analysis
Variability fingered as next design pothole
On-chip variation and timing closure
Leakage takes priority at 65nm
Variability upends designers' plans

Altos is an EDA company that provides ultra fast characterization technology to enable IP reuse via accurate modeling of timing, noise, power and process variation.

06.14.10 Concept Engineering's Nlview Visualization Engine Adopted by Altos Design Automation to Power New Debug and Process Control GUI
06.14.10 Altos Expands into China, Doubles Headquarters Space, Adds Worldwide Sales VP
06.10.10 Altos and Extreme DA Team to Create Accurate Industry Standard CCS Noise Models

Other 2010 Press Releases

05.10.10 Netlogic Microsystems Utilizes Altos' Liberate MX for Embedded Memory Characterization on 40nm Tapeout
03.08.10 Imec and Altos collaborate on chip design and prototyping service

2009 Press Releases

12.14.09 Altos Release Variety MX for Statistical Memory Characterization
(View datasheet)
07.15.09 Altos Launches Liberate MX for Fast and Accurate Memory Characterization
(View datasheet, White paper)
07.15.09 CSR Adopts Liberate LV for Library Validation
07.15.09 Altos Announces Liberate LV for Comprehensive Library Validation
(View datasheet)
07.15.09 EdXact and Altos Partner to Improve Characterization Performance
03.02.09 Altera Adopts Altos Liberate Cell Characterization for Hardcopy ASIC's
01.23.09 Altos Forms Pal O’Altos Partner Program to Foster IC Yield Improvement and Power Reduction

2008 Press Releases

07.28.08 Altos Variety LX Adopted by STMicroelectronics for ultra-fast Corner and Statistical Characterization at 40nm
06.09.08 Altos Releases Variety LX to enable ultra-fast Corner and Statistical Characterization for 45nm and below
06.05.08 Altos Statistical Timing Models Proven on UMC's 65nm Process
06.03.08 Altos Cell Characterization Tools Used for TSMC's 40nm Libraries

Old Press Releases...

Improve Your View...

Liberate and Variety Demos

DAC 2010 : "Enabling a World of IP"

Audio interview with Jim McCanny, Altos CEO on Edacafe May 2010

Interview with Jim McCanny, Altos CEO at EDSFair Jan 2009

News and Articles
02.26.10 Thanks for the Memories But...
08.18.09 Designers - Start Your Characterization Engines
02.24.09 20 Electronics Industry Leaders Collaborate to Accelerate Development and Adoption of Design for E-Beam Technology
01.21.08 EDACafe: Fireside Chat: Rick Lucier & Jim McCanny
12.05.07 SCDsource: The 'Inconvenient Truth' of statistical design
03.01.07 Chip Design: Where's the value in DFM? D or M?
01.15.07 EEtimes: Statistical timing gets modeling boost
01.15.07 EDN: Characterization tool aids SSTA-library creation
01.08.07 EEtimes: Altos closes $1.5M, signs Jim Hogan
07.25.06 EEtimes: Firms partner on standard statistical analysis library format
07.17.06 EEtimes: What's Hot at DAC?
07.03.06 EEtimes: Startup to 'Liberate' library characterization
07.03.06 EEtimes: Statistical timing revs for 45-nm era
07.03.06 ElectronicNews: Altos Targets Statistical Timing Models
Copyright © 2008
Altos Design Automation Inc.
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