Altos is an EDA company that provides ultra fast characterization technology to address key nanometer challenges such as low power, yield and process variation.

Visit us at DAC (Booth #1504) in San Francisco, July 27th-30th

To schedule a demo and presentation please contact us via phone or email.

03.02.09	Altera Adopts Altos Liberate Cell Characterization for Hardcopy ASIC's
01.23.09	Altos Forms Pal O’Altos Partner Program to Foster IC Yield Improvement and Power Reduction

2008 Press Releases

07.28.08	Altos Variety LX Adopted by STMicroelectronics for ultra-fast Corner and Statistical Characterization at 40nm
06.09.08	Altos Releases Variety LX to enable ultra-fast Corner and Statistical Characterization for 45nm and below
06.05.08	Altos Statistical Timing Models Proven on UMC's 65nm Process
06.03.08	Altos Cell Characterization Tools Used for TSMC's 40nm Libraries

2007 Press Releases

10.23.07	Altos and Extreme DA Create Proven Variation-Aware Statistical Design Flow
09.30.07	Altos and Cadence Qualify Statistical Timing Models for 45nm and 65nm Processes
06.28.07	TSMC Reference Flow 8.0 Includes Altos' Variety
06.04.07	Intrinsity deploys Altos' Liberate to create libraries for signal integrity analysis
06.04.07	Si2 Open Modeling Coalition Approves Statistical Format Extensions
05.07.07	Global Unichip adopts Altos' Liberate to strengthen its service on low power applications
04.04.07	Synopsys Enhances Library Compiler to Put Current-Source Models Within Reach of Every Designer
03.26.07	STARC adopts Altos' Characterization Products for their STARCAD-CEL Design Methodology
01.15.07	Altos Design Automation Inc. Releases Variety, a High Speed, Statistical Cell Library Characterizer
01.15.07	Si2 Open Modeling Coalition Gains Access to Statistical Library Characterization Tool from Altos Design Automation
01.08.07	Altos closes $1.5M First Round of Funding
2006	Old Press Releases...

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Liberate and Variety Demos

Interview with Jim McCanny, Altos CEO at EDSFair Jan 2009

News and Articles

02.24.09	20 Electronics Industry Leaders Collaborate to Accelerate Development and Adoption of Design for E-Beam Technology
01.21.08	EDACafe: Fireside Chat: Rick Lucier & Jim McCanny
12.05.07	SCDsource: The 'Inconvenient Truth' of statistical design
03.01.07	Chip Design: Where's the value in DFM? D or M?
01.15.07	EEtimes: Statistical timing gets modeling boost
01.15.07	EDN: Characterization tool aids SSTA-library creation
01.08.07	EEtimes: Altos closes $1.5M, signs Jim Hogan
07.25.06	EEtimes: Firms partner on standard statistical analysis library format
07.17.06	EEtimes: What's Hot at DAC?
07.03.06	EEtimes: Startup to 'Liberate' library characterization
07.03.06	EEtimes: Statistical timing revs for 45-nm era
07.03.06	ElectronicNews: Altos Targets Statistical Timing Models